Manufacturing method of semiconductor device

ABSTRACT

After deposition of a conductor film made of titanium tungsten over a main surface of a semiconductor substrate formed with grooves, an initial conductor film made of aluminium is further deposited. Subsequently, the conductor film is made to reflow and run into the grooves. Thereafter, while heating, further conductor films are respectively deposited, thereby causing these conductor films to run into the grooves. The provision of the initial conductor film suppresses or prevents aluminium in the further conductor films and silicon in the semiconductor substrate from reacting with each other during reflowing of the conductor films.

BACKGROUND OF THE INVENTION

The present invention relates to a technique for use in the manufactureof a semiconductor device; and, more particularly, the invention relatesto a technique that is effective for application to a wiring processthat includes a step of burying a conductive film, that is made mainlyof aluminium (Al), inside an opening for wiring.

The wiring technique studied by us is, for example, as set out below.Initially, an opening for wiring is formed in a semiconductor substrate,after which a titanium (Ti) film, for example, is deposited on thesemiconductor substrate, including the inside of the wiring opening.Subsequently, an aluminium film, for example, is deposited on thetitanium film at low temperatures and high power to a relatively largethickness (e.g. about 200 nm). Thereafter, the semiconductor substrateis maintained at high temperatures (e.g. about 400° C.) until thealuminium film is deposited to a desired thickness (e.g. about severalhundreds of nanometers). The high temperatures are kept continuouslyover several minutes to cause reflow of the aluminium film, therebycausing the opening to be buried therewith.

A wiring technique is set out, for example, in Japanese Laid-open PatentApplication No. 2001-267569. In this application, a technique isdisclosed wherein a source electrode of a power MOSFET (Metal OxideSemiconductor Field Effect Transistor) is constituted of a barrier layerthat is made, for example, of titanium tungsten, titanium nitride (TiN)or the like, and this barrier layer is built up with pure aluminiumthereon, so as to prevent a failure from occurring upon ultrasonic wirebonding.

SUMMARY OF THE INVENTION

We have found that the wiring technique studied by us has the followingproblems. If the amount of buried aluminium inside the opening forwiring increases, then it becomes necessary to heat the aluminium tohigher temperatures so as to enhance the reflowability of the aluminium.Nevertheless, the barrier properties of titanium are not satisfactory,so that when the heating temperature exceeds, for example, about 400°C., a reaction between the aluminium and silicon (Si) proceeds, withsome possibility that a junction leakage failure will occur.

An object of the present invention is to provide a technique that iscapable of improving the reliability of semiconductor devices.

The above and other objects and novel features of the present inventionwill become apparent from the following description, when taken withreference to the accompanying drawings.

A typical embodiment of the invention, among those embodiments disclosedin this application, will be briefly described below.

According to the invention, there is provided a method of manufacture ofa semiconductor device, which method comprises the steps of: depositing,on a semiconductor substrate including an opening for wiring, a firstconductive film having a structure that is capable of suppressing orpreventing a reaction from occurring between an aluminium atom and aconstituent atom of the semiconductor substrate upon thermal treatmentfor re-melting of the conductive film, which is made mainly ofaluminium; and thermally treating the conductor film made mainly ofaluminium after, or in the course of deposition thereof, untilre-melting occurs, thereby causing the aluminium-based conductor film toflow and run into the opening for wiring.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of the structure during a step in the processof manufacture of a semiconductor device according to one embodiment ofthe invention;

FIG. 2 is a sectional view of the structure during a step in the processof manufacture of the semiconductor device, subsequent to the step ofFIG. 1;

FIG. 3 is a sectional view of the structure during a step in the processof manufacture of the semiconductor device, subsequent to the steps ofFIG. 2;

FIG. 4 is a sectional view of the structure during a step in the processof manufacture of the semiconductor device, subsequent to the steps ofFIG. 3;

FIG. 5 is an enlarged, sectional view of the part A of FIG. 4;

FIG. 6 is a flowchart of the process for burying a groove formed in themanufacture of the semiconductor device of FIG. 4;

FIG. 7 is an enlarged, sectional view of the part A in the course ofmanufacture of the semiconductor device, subsequent to the step of FIG.4;

FIG. 8 is an enlarged, sectional view of the part A in the course ofmanufacture of the semiconductor device, subsequent to the step of FIG.7;

FIG. 9 is an enlarged, sectional view of the part A in the course ofmanufacture of the semiconductor device, subsequent to the step of FIG.8;

FIG. 10 is an enlarged, sectional view of the part A in the course ofmanufacture of the semiconductor device, subsequent to the step of FIG.9;

FIG. 11 is an enlarged, sectional view of the part A in the course ofmanufacture of the semiconductor device, subsequent to the step of FIG.10;

FIG. 12 is an enlarged, sectional view of the part A in the course ofmanufacture of the semiconductor device, subsequent to the step of FIG.11;

FIG. 13 is an enlarged, sectional view of the part A in the course ofmanufacture of the semiconductor device, subsequent to the step of FIG.12;

FIG. 14 is an enlarged, sectional view of the structure during a step inthe process of manufacture of the semiconductor device, subsequent tothe step of FIG. 13;

FIG. 15 is a top plan view of the structure during a step in the processof manufacture of a semiconductor device according to another embodimentof the invention;

FIG. 16 is a section, taken along the line X1-X1 of FIG. 15;

FIG. 17 is an enlarged, sectional view of the structure during a step inthe process of manufacture of the semiconductor device, subsequent tothe step of FIG. 16;

FIG. 18 is an enlarged, sectional view of the structure during a step inthe process of manufacture of the semiconductor device, subsequent tothe step of FIG. 17;

FIG. 19 is a top plan view of the structure during a step in the processof manufacture of a semiconductor device according to a furtherembodiment of the invention;

FIG. 20 is a section, taken along the line X2-X2 of FIG. 19;

FIG. 21 is an enlarged, sectional view of the structure during a step inthe process of manufacture of the semiconductor device, subsequent tothe step of FIG. 20;

FIG. 22 is an enlarged, sectional view of the structure during a step inthe process of manufacture of the semiconductor device, subsequent tothe step of FIG. 21; and

FIG. 23 is a sectional view of the structure during a step in theprocess of manufacture of a semiconductor device according to a stillfurther embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Although embodiments of the invention are illustrated by division of thesubject matter into a plurality of sections or sub-embodiments, ifexpediently necessary, these divisions are not to be taken as beingmutually irrelevant to one another, unless otherwise stated. Moreparticularly, one division may be in a relation with a modification,details, supplemental explanation and the like of part or all of theothers. In the following description of the embodiments, where referenceis made to a number and other parameters of elements (including thenumber, numerical value, quantity, range and the like), they should notbe construed as being limited to specified values or numbers,respectively, except for the case where they are otherwise specified orlimited to a specific value apparently in principle. That is, thosevalues smaller than or larger than the respective specified values mayalso be within the scope of the invention.

Moreover, it is as a matter of course that constituent elements(including steps) in the following embodiments are not always essential,except in the case where otherwise specified or where such elements areconsidered to be apparently essential in principle. Likewise, ifreference is made to the shape, position, relation and the like of theconstituent elements, then substantially the same or similar shapes andthe like are also within the scope of the invention, except for the casewhere they are otherwise specified or where such shapes should not beapparently included as a matter of principle. This is true of theabove-indicated numbers and ranges as well.

Throughout the drawings illustrating the embodiments of the invention,like reference numerals indicate like parts or members having the samefunction, which parts or members are not repeatedly explained after oncehaving been explained.

In the description of the embodiments of the invention, by theexpression, for example, “composed or made of aluminium”, it is intendedthat aluminium is used as a main component. In general, it is assumedthat highly pure aluminium contains impurities, and, thus, a membermade, for example, of aluminium should not be construed as excluding theinclusion of additives or impurities therein. This is not limited toaluminium, but is applied to other types of metals and the like (such astitanium tungsten, tungsten, tantalum, nitrides thereof, and tungstensilicide or its nitride).

The embodiments of the invention will be described in detail withreference to the accompanying drawings.

(Embodiment 1)

A semiconductor substrate in accordance with Embodiment 1 has, forexample, a n-channel power MISFET (Power Metal Insulator SemiconductorField Effect Transistor: power transistor) having a trench gatestructure. An example of a method of manufacture of a semiconductordevice according to Embodiment 1 of the invention will be described withreference to FIGS. 1 to 14.

FIG. 1 is a sectional view of the structure during manufacture of thesemiconductor device of Embodiment 1. The semiconductor device(hereinafter referred to simply as a substrate) is in the form of aso-called epitaxial wafer (hereinafter referred to simply as a wafer)having, for example, a structure in which an n⁻ type semiconductor layer1 b is deposited on an n⁺ semiconductor layer 1 a using an epitaxialtechnique. The semiconductor layers 1 a, 1 b are made, for example, ofsingle crystal silicon (Si), respectively. The impurity concentration inthe semiconductor layer 1 a is, for example, at about 2.0×10¹⁹ cm⁻³, andthat of the semiconductor layer 1 b is, for example, at about 1.0×10¹⁶cm⁻³.

The semiconductor layer 1 b is formed with a p⁻ type semiconductorregion 2 (well: first semiconductor region) therein. This semiconductorregion 2 has channels for a plurality of power MISFET's (hereinafterreferred to simply as power MIS('s) to be formed therein. Thesemiconductor region 2 is formed, for example, by distributing boron (B)from the main surface of the semiconductor layer 1 b to an intermediateposition along the thickness of the semiconductor layer 1 b. The peakconcentration of the impurity in the semiconductor region 2 is set, forexample, at about 1×10¹⁶ to about 1×10¹⁸ cm⁻³.

A p-type semiconductor region (well) 3 is formed along the outerperipheral end of the semiconductor region 2 in the semiconductor layer1 b. Boron, for example, is contained in this semiconductor region 3. Anisolation region 4 that is made, for example, of silicon oxide (SiO₂ orthe like) is formed, according to a LOCOS (Local Oxidization of Silicon)technique or the like, at the isolation region in the main surface ofthe semiconductor layer 1 b. The isolation region 4 may be in the formof a groove (trench isolation).

The active region surrounded by the isolation region 4 becomes a powerMID-forming region. This active region is formed with a plurality ofgrooves (first grooves) 5 therein. The grooves 5, respectively, areprovided for every cell, and they extend from the main surface of thesemiconductor layer 1 b to an intermediate position in the direction ofthe depth of the semiconductor layer 1 b, as viewed in section, and theyextend along a certain direction as viewed in plane view. The inner wallsurfaces of the groove 5 and the upper surface of the semiconductorlayer 1 b at an area around the opening of the groove 5 have a gateinsulating film 6, that is made, for example, of silicon oxide, formedthereon.

A trench-type gate electrode 7 of the power MIS is formed on the gateinsulating film 6. The gate electrode 7 is made, for example, of a lowresistance polysilicon film and is shaped in the form of a T in section.More particularly, the gate electrode 7 has a first portion 7 a that isburied inside the groove, from which it is separated by the gateinsulating film 6, and a second portion 7 b that joins the first portion7 a, projects outwardly from the groove and has a width greater than thewidth of the groove 5 (i.e. the width along a minor direction).

At the outer periphery of the power MID-forming region, an extrinsicgate wiring 7L is formed on the main surface of the semiconductor layer1 b, from which it is spaced by the gate insulating film 6 and theisolation region 4. The extrinsic gate wiring 7L is integrally formedwith the respective gate electrodes 7 and is to be electricallyconnected therewith. A cap insulating film (first insulating film) 8,which is made, for example, of a silicon oxide film, is deposited, afterpatterning, over the gate electrodes 7 and the extrinsic gate wiring 7L.

An n-type semiconductor region (second semiconductor region) 9 a,serving as a source, is formed at a portion of the semiconductor layer 1b that is established between adjacent gate electrodes 7. Thissemiconductor region 9 a is formed by distributing, for example, arsenic(As) from the main surface of the semiconductor layer 1 b to anintermediate position along the depth of the semiconductor region 2,which processing has been already carried out prior to the formation ofthe groove 5. The peak concentration of the impurity in thesemiconductor region 9 a is, for example, about 1×10¹⁸ to about 1×10²⁰cm⁻³.

FIGS. 2 and 3 are, respectively, sectional views of the structure duringthe manufacture of the semiconductor device, subsequent to the stepshown in FIG. 1. As shown in FIG. 2, a resist pattern covering regionsother than the source region is formed over the main surface of thesubstrate 1 of FIG. 1, after which arsenic, for example, is ionimplanted into the main surface of the substrate 1 through the mask ofthe resist pattern to form an n-type semiconductor region (secondsemiconductor region) 9 for the source on the surface layer of thesemiconductor layer 1 b between adjacent gate electrodes 7.Subsequently, an insulating film 10, that is made, for example, ofsilicon oxide or the like, is deposited over the main surface of thesemiconductor layer 1 b of the substrate (wafer) 1 by a CVD (ChemicalVapor Deposition) method, followed by formation of a photoresist pattern(hereinafter referred to as a resist pattern) thereon, so that the outerperipheral region of the power MIS-forming region is covered therewith,but others are exposed. In this condition, the insulating film 10 on thesubstrate 1 is etched back using an anisotropic dry etching technique toform the respective electrodes 7 at the power MIS-forming region andside walls (second insulating films) 10 a at the side surfaces of thecap insulating films 8, along with an insulating film 10 b being formedaround the power MIS-forming region.

Subsequently, as shown in FIG. 3, the cap insulating films 8, side walls10 a and insulating film 10 b are used as an etching mask to etch theexposed portions of the semiconductor layer 1 b using a dry etchingtechnique, so as to form grooves (second grooves) 11. The respectivegrooves 11 extend from the main surface of the semiconductor layer 1 bto an intermediate position along the depth of the semiconductor region2, as viewed in section, and they also extend along a given direction,as viewed in plane view. Thereafter, boron difluoride (BF₂), forexample, is ion implanted into the semiconductor layer 1 b at 80 keV andabout 3×10¹⁵ cm⁻², thereby forming a p⁺-type semiconductor region (thirdsemiconductor region) 12 at the bottom of the groove 11.

FIG. 4 is a sectional view of the structure during the manufacture ofthe semiconductor device, subsequent to the step shown in FIG. 3. FIG. 5is an enlarged, sectional view of region A in FIG. 4. In this step, thesubstrate 1 is subjected to wet etching to slightly etch the exposedsurface portions of the insulating film 10 and the gate insulating film6 in such a way that the side surface of the side wall 10 a is recessedfrom the side surface of the groove 11. In this way, part of the mainsurface of the semiconductor layer 1 b around the opening of the groove11 is exposed. This contributes to an increase in the contact areabetween the source electrode and the semiconductor source region 9 a.The above-mentioned etching permits a groove (second groove) 13 to beformed, which groove is located above and is wider than the groove 11and runs into the groove 11.

As shown in FIG. 5, the total depth D1 of the grooves 11, 13 is, forexample, about 1.2 μm, and the depth D2 of the groove 11 is, forexample, 0.4 μm. The depth D3 of the groove 13 is, for example, about0.8 μm, and the width D4 of the groove 11 is, for example, about 0.5 to0.6 μm. In this connection, however, the wiring formation method ofEmbodiment 1, as described hereinafter, may also be applied to the casewhere no etching is carried out for the purpose of the formation of thegroove 13, i.e., the case of a structure wherein the groove 13 is soarranged that its width is not larger than, but is equal to that of, thegroove 11. After completion of the etching, ordinary photolithographicand dry etching techniques using a resist pattern as a mask areperformed to form a contact hole 14, so that part of the extrinsic gatewiring 7L is exposed at the insulating film 10 b and the cap insulatingfilm 8.

Such grooves 11, 13 as formed in the power MIS are, respectively, largerin width than a typical contact hole or through-hole of a semiconductordevice having an ordinary logic circuit or memory circuit, with thetendency that the aspect ratio increases owing to a reduction in sizebetween adjacent cells accompanied by the requirement for improving thedegree of integration of the cells of a power MIS. In order to bury suchrelatively great, deep grooves 11, 13 with an aluminium (Al) film, it isdesirable to raise the reflow temperature after or during deposition ofthe aluminium film. Nevertheless, if the reflow temperature increases,and in particular, if it exceeds 400° C., the reaction between thealuminium used as a wiring material and the silicon in the substrate 1proceeds, with the attendant problem that a junction failure takes placeat the channel portion of the power MIS. On the other hand, there is aproblem as to how the grooves 11, 13, respectively, can be buried in aspace-free, continuous condition so as to lower the ON resistance (i.e.ON resistance between the source electrode and the drain electrode) ofthe power MIS. To cope with this problem, the following procedure isperformed according to Embodiment 1.

FIG. 6 is a flow chart of the process for burying the grooves 11, 13.FIGS. 7 to 13, respectively, are enlarged, sectional views showing aportion corresponding to the region A of FIG. 4 in the course of themanufacture of the semiconductor device, according to the respectivesteps of the flow chart of FIG. 6.

As shown in FIG. 7, a conductor film (first conductor film) 15 a isdeposited on the main surface of the substrate (wafer) 1 (step 100 inFIG. 6). This permits a thin conductor film 15 a to be deposited on theinner surfaces (inner wall surfaces and bottom surface) of the grooves11, 13 and the contact hole 14 (see FIG. 4), so that the grooves 11, 13and the contact hole 14 are not buried completely. This conductor film15 a has a barrier function for suppressing or preventing the aluminiumused as a main wiring material, as will be described hereinafter, fromdiffusing into the aluminium film side, and it also prevents the siliconof the semiconductor layer 1 b from diffusing into the side of thealuminium film used as the main wiring material. Especially, inEmbodiment 1, if the reflow of aluminium, as will be describedhereinafter, is carried out at high temperatures, for example, 400° C.or over, the conductor film 15 a is considered to provide a structure(from the aspects of material, thickness, function and the like) that iscapable of suppressing or preventing a reaction from occurring betweenthe aluminium used as a main wiring material and the silicon in thesemiconductor layer 1 b.

According to our studies, it has been found that where titanium (Ti) isselected as a material for the conductor film 15 a, the resultanttitanium film is converted to a silicide thereof substantially entirelyalong the thickness direction thereof when subjected to annealing afterthe deposition thereof. Eventually, when aluminium used as a main wiringmaterial is deposited and subjected to reflow treatment at hightemperatures (400° C. or over), the reaction between the aluminium andthe silicon proceeds, thus leading to a junction leakage failure at thechannel portion of power MIS. In order to suppress or prevent a reactionfrom occurring between the aluminium and the silicon, as mentionedabove, the conductor film 15 a should be made of a high heat resistancematerial, which is not converted into a silicide entirely along thethickness of the conductor film 15 a by annealing subsequent to thedeposition of the conductor film 15 a. In other words, the conductorfilm 15 a is so selected as to provide a structure wherein the silicidelayer is formed only at a portion in contact with the semiconductorlayer 1 b; and, thus, the conductor film 15 a is interposed between thesilicide layer and the aluminium film that is used as a main wiringmaterial in order to prevent direct contact between the silicide layerand the aluminium that is used as a main wiring material. In thismanner, if the thermal treatment temperature of the aluminium that isused as a main wiring material, as will be described hereinafter, ismade high, the reaction between the aluminium and the silicon in thesubstrate 1 can be suppressed or prevented by means of the conductorfilm 15 a. Accordingly, the main wiring material of aluminium can bethermally treated at high temperatures, and, thus, the grooves 11, 13can be buried with aluminum in an efficiently improved manner.

As a specific material for the conductor film 15 a, a number ofmaterials could be selected, of which titanium tungsten (TiW) is mostpreferred. Titanium tungsten has favorable properties in that itexhibits a low reactivity with silicon, is thermally stable and low inheat resistance, and is low in contact resistance and electricalresistance, because this material is a kind of metal. Where titaniumtungsten is selected as a material for the conductor film 15 a, itsthickness is, for example, at about 200 nm. It will be noted that the“thickness” of the conductor film 15 a refers to a design thickness(which is substantially equal to the thickness of the conductor film 15a that is deposited on the upper surface of the cap insulating film 8and the insulating film 10 b). The thickness of the conductor film 15 aattached on the side walls and the bottom surfaces of the grooves 11, 13becomes smaller than the design thickness (of about 200 nm) (the term“design thickness” used hereinafter has the same meaning as set outabove).

Other types of materials for the conductor film 15 a include, forexample, high-melting metals, such as tungsten (W), tantalum (Ta) andthe like. In this case, they are high in heat resistance and are low incontact and electrical resistances, because of the nature of the metalthereof. Further types of materials for the conductor film 15 a include,for example, high melting metal nitride films, such as a titaniumtungsten nitride film (TiWN), a tungsten nitride film (WN), a tantalumnitride film (TaN) and the like. Still further types of materials forthe conductor film 15 a include, for example, tungsten silicide (WSi₂)and a nitride thereof (WSiN). Where tungsten suicide (WSi₂) or itsnitride (WSiN) is selected, silicon is present in the conductor film 15a. The bonding between tungsten and silicon is stronger than the bondingbetween aluminium and silicon, so that the reactivity between aluminiumand silicon becomes low. As a result, substantially similar effects areobtained as in the case where titanium tungsten is selected. Using suchmaterials as indicated above or other types of materials as theconductor film 15 a, proper control of the thickness of the conductorfilm 15 a may cause such action and effect as set out hereinabove.

Next, the substrate (wafer) 1 is annealed in an atmosphere of an inertgas, such as, for example, nitrogen gas (N₂) or the like, at 650° C. forabout 30 minutes (step 101 in FIG. 6). As shown in FIG. 8, this permitsa very thin silicide layer (compound layer) 15 b, that is made, forexample, of titanium silicide (TiSi₂) or the like, to be formed at theinterface of the contact surface of the conductor film 15 a with thesemiconductor layer 1 b and the extrinsic gate wiring 7L (see FIG. 4).

In Embodiment 1, the conductor film 15 a is not wholly converted to asilicide, as mentioned above, but the silicide layer 15 b is formed onlyat the interface portion of contact between the conductor film 15 a andthe semiconductor layer 1 b, with the conductor layer 15 b being left atthe upper layer or portion thereof. The contact resistance between thesource electrode and the semiconductor region for the source, to bedescribed hereinafter, can be reduced through the formation of such asilicide layer 15 b, thus enabling the ON resistance of the power MID tobe reduced. This treatment likewise can be carried out for the casewhere the conductor film 15 a is made of a material other than titaniumtungsten. In this case, a silicide layer is formed only at a contactportion between the conductor film 15 a and the semiconductor layer 1 b,like the case using titanium tungsten, with the conductor film 15 abeing left at an upper layer relative to the silicide layer.

Subsequently, as shown in FIG. 9, a conductor film (second conductorfilm) 15 c made of a high-melting metal film, such as titanium (Ti) orthe like, is deposited, for example, to a design thickness of about 50nm by a sputtering method (see step 102 in FIG. 6). In doing so, theconductor film 15 c is so attached as to cover the surface of theconductor film 15 a at the inner surface (including the inner wallsurfaces and bottom surfaces) of the grooves 11, 13 and the contact hole14 without fully burying the grooves 11, 13 and the contact hole 14 (seeFIG. 4) therewith. This conductor film 15 c has the functions ofimproving the wettability of an aluminium film to be subsequentlydeposited and suppressing or preventing aluminium and silicon fromreacting with each other. The conductor film 15 formed of theabove-stated conductor films 15 a, 15 b, 15 c is an auxiliary wiringmaterial for forming the gate electrode and the source electrode of thepower MIS.

Next, as shown in FIG. 10, a conductor film that is made, for example,of aluminium (an aluminium-based conductor film made mainly of aluminiumor a first aluminium-based conductor film made mainly of aluminium) 16 ais deposited on the main surface of the substrate (wafer) 1 by asputtering method (step 103 in FIG. 6). This conductor film 16 a servesas an underlying film having the function of ensuring the continuity ofan aluminium film to be formed in a subsequent deposition procedure ofhot aluminium, and it is formed as a film at a low temperature (e.g. anormal temperature: 30° C.).

More particularly, when an aluminium film is deposited, under hightemperature conditions, on the conductor film 15 c that is made oftitanium or the like, small lumps of aluminium are formed on the surfaceof the conductor film 15 c, thus not ensuring the continuity of thealuminium film. In order to establish the continuity of an aluminiumfilm, a conductor film 16 a that is made of an aluminium film is formedunder low temperature conditions prior to the formation of an aluminiumfilm under high temperature conditions.

The thickness of the conductor film 16 a is at a level sufficient tobury the groove 11 of a relatively small width, and, more particularly,at such a level that the portion of the conductor film 15 c is notexposed at the corner (i.e. a portion formed at the intersection betweenthe main surface of the semiconductor layer 1 b and the side surface ofthe groove 11) of the semiconductor layer 1 b around the opening of thegroove 11. This is provided for the reason that, if part of theconductor film 15 c is exposed, the continuity of a subsequentlydeposited aluminium film cannot be ensured. The design thickness of theconductor film 16 a formed in this way is, for example, at about 400 nm.At this stage, the conductor film 16 a is in such a state as to beattached through the thin conductor films 15 a, 15 b, 15 c on the innersurfaces (i.e. the inner wall surfaces and bottom surfaces) of thegrooves 11, 13 and the contact hole 14 without completely burying thegroove 13 and the contact hole 14 (FIG. 4) therewith.

After the deposition of the conductor film 16 a, the substrate (water) 1is annealed, as shown in FIG. 11, within a sputtering apparatus whereinthe conductor film 16 a has been deposited, thereby causing theconductor film 16 a to be made to reflow (see step 104 in FIG. 6). Inthis manner, the conductor film 16 a is made to flow and run into thegrooves 11, 13. At this stage, the annealing temperature is set at atemperature, for example, that is higher than about 400° C., inEmbodiment 1. More particularly, annealing is carried out, for example,at 450° C. for several minutes. This enables the reflow property of thealuminium to be improved. More particularly, a great quantity ofaluminium is charged or caused to run into the grooves 11, 13, which arefine and have a high aspect ratio, thereby burying the grooves 11, 13satisfactorily. This permits the electrical resistance within thegrooves 11, 13 to be reduced and thus, the ON resistance of the powerMID can be reduced, making it possible to improve the performance of thepower MIS.

As stated hereinabove, in Embodiment 1, the conductor 15 a is formed sothat even if the annealing temperature is set at a level, for example,of higher than 400° C., the reaction between the aluminium and thesilicon in the semiconductor layer 1 b can be suppressed or prevented.Thus, the occurrence of junction failure at the channel portion of thepower MIS ascribed to the reaction can be suppressed or prevented, withthe possibility of improved yield and increased reliability of the powerMIS.

At this stage, the conductor film 16 a does not completely bury thegrooves 11, 13 and the contact hole 14 (see FIG. 4) therewith, but is ina state of being attached to the inner surfaces (i.e. the inner wallsurfaces and bottom surfaces) of the grooves 11, 13 and the contact hole14 through the thin conductor films 15 a, 15 b, 15 c. A recess is leftat the upper surface of the conductor film 16 a within the groove 13.Thereafter, a conductor film (second aluminium-based conductor film) 16b made, for example, of aluminium or the like is deposited, as shown inFIG. 12, by a sputtering method at a low rate within the same sputteringapparatus as used for the deposition of the conductor film 16 a (step105 in FIG. 6). At this time, the conductor 16 b is deposited whileheating the substrate (wafer) 1 from the back side thereof (so-calledheat sputtering). In this way, the conductor films 16 a, 16 b flow andrun into the grooves 11, 13. The heating temperature is set, forexample, at a level of higher than 400° C., and, more particularly, at atemperature as high as about 450° C. Eventually, a similar effect as inthe case of the conductor film 16 a can be obtained.

The deposition rate of the conductor film 16 b should be lower than thedeposition rate of an aluminium film to be subsequently deposited. Thisis because the recessed portion in the groove 13 is well buried with theconductor film 16 b, while ensuring the continuity of the conductor film16 b. The deposition rate of the conductor film 16 b is, for example,0.4 μm per unit time (of about several minutes). The design thickness ofthe conductor film 16 b that is deposited at this stage is about half ofthe width D3 (see FIG. 5) of the groove 13, and it is particularly, forexample, about 400 nm. This permits the remaining recess in the groove13 to be substantially completely buried with the conductor film 16 b.It will be noted that, although a boundary line between the conductorfilms 16 a, 16 b is indicated by a broken line in FIG. 12, thisindication is provided only for the sake of ease in viewing the drawing,and such a boundary line is not actually formed.

Thereafter, as seen in FIG. 13, a conductor film (second aluminium-basedconductor film) 16 c, that is made, for example, of aluminium or thelike, is deposited on the main surface of the semiconductor substrate(wafer) 1 at a high rate according to a sputtering method within thesame sputtering apparatus as used for the deposition of the conductorfilm 16 b (step 106 in FIG. 6). In this case, the conductor film 16 c isdeposited while heating the substrate (wafer) 1 from the back sidethereof. The heating temperature is set, for example, at a level ofhigher than 400° C., and, it is particularly, for example, about 450° C.In this way, similar effects as in the case of the conductor films 16 a,16 b can be obtained.

The deposition rate of the conductor film 16 c is made higher than thedeposition rate of the conductor film 16 b. This is for the reason that,at this stage, the groove 13 is substantially completely buried with theconductor film 16 b, so that priority is put on the shortage indeposition time of the aluminium film over the burying property andcontinuity of the groove being ensured, thereby improving thethroughput. The deposition rate of the conductor film 16 c is, forexample, about 4.1 μm per unit time (of about several minutes, which isthe same as the unit time for the deposition rate of the conductor film16 b). The thickness of the conductor film 16 c deposited that isdeposited at this time should be sufficient to lower the ON resistanceof the power MIS and is particularly as thick as about 4.1 μm, forexample.

The conductor film formed of the thus deposited conductor films 16 a, 16b, 16 c, each made mainly of aluminium, is used as the afore-mentionedmain wiring material for forming gate and source electrodes. At thisstage, the grooves 11, 13 and the contact hole 14 (see FIG. 4) are,respectively, buried with the conductor film 16 to a full extent.

According to this Embodiment 1, the aluminium-based conductor film 16that is made mainly of aluminium can be buried in the grooves 11, 13,which are greater in size than the grooves or holes typically formed inordinary semiconductor devices, and, thus, they have a high aspectratio, in a space-free condition and can also be deposited so as to bethick in the state of ensuring continuity. This enables the ONresistance of the power MID to be lowered, thus permitting a greatcurrent to pass without exceeding the maximum power loss (drain loss) ata specified reference point temperature. Thus, the performance andreliability of the semiconductor device can be improved.

If the grooves 11, 13 are microfabricated, such grooves 11, 13 can bewell buried with the conductor film 16. Thus, the microfabrication ofthe grooves 11, 13 can be promoted, and the degree of integration of thecells of the power MIS can be improved. Accordingly, the number of cellsformed in a power MIS per unit area can be increased, thus leading to animproved capacity of the semiconductor device. It will be noted that,although boundary lines of the conductor films 16 a, 16 b, 16 c are,respectively, indicated by a broken line in FIG. 13, such indication isprovided only for the sake of ease in viewing the drawing, and theseboundary lines are not formed actually.

FIG. 14 is a sectional view of the structure in the manufacture of thesemiconductor device, subsequent to the step shown in FIG. 13. In thisstep, the conductor films 16, 15 are, respectively, patterned byordinary photolithographic and dry etching techniques to form a gateelectrode 17 and a source electrode 18, each having the conductor films16, 15, on the main surface of the substrate 1. The gate electrode 17 iselectrically connected to the extrinsic gate wiring 7L via the contacthole 14, and the source electrode is electrically connected to thesemiconductor regions 2, 9, 12 of the semiconductor layer 1 b via thegrooves 13, 11.

After deposition of a surface protective film on the main surface of thesubstrate 1, a bonding area thereof is removed by etching to form abonding pad. Thereafter, the substrate (wafer) 1 is polished on the backsurface thereof, and a drain electrode is formed at the back surface.Subsequently, a semiconductor device having a power MIS is manufacturedthrough an ordinary assembling procedure of the semiconductor device.This power MIS is so arranged that, in a state where a positive voltageis applied to the drain electrode and a ground voltage (0 V) is appliedto the source electrode 18, the power MIS commences to work when apositive voltage is applied to the gate electrode 17 from a state wherethe gate electrode 17 has been supplied with the ground voltage and,thus, does not work. When a positive voltage is applied to the gateelectrode 17, an inversion layer (n-channel) is formed in the p⁻-typesemiconductor region 2, under which the n-type semiconductor region 9for the source and the semiconductor layers 1 a and 1 b for the drainare connected through the inversion layer. As a result, electrons passfrom the source electrode 18 to the drain electrode at the back surfaceof the substrate 1 via the n-type semiconductor region 9, inversionlayer, semiconductor layer 1 b and semiconductor layer 1 a on the mainsurface of the substrate 1. More particularly, an electric currentpasses from the drain electrode to the source electrode 18, so that thepower MIS is turned on. In this way, the drain current of the power MIDruns along the thickness of the substrate. On the other hand, when thegate voltage is changed from a positive voltage to a ground or negativevoltage, the above-mentioned inversion layer disappears, so that noelectric current passes between the n-type semiconductor region 9 andthe semiconductor layers 1 a, 1 b, rendering the power MIS off.

(Embodiment 2)

In Embodiment 2, an application to a Damascene wiring formationtechnique is illustrated with reference to FIGS. 15 to 18. FIG. 15 is aplan view of the structure in the manufacture of a semiconductor deviceof Embodiment 2, and FIG. 16 is a section taken along the line X1-X1 inFIG. 15. FIGS. 17 and 18 are, respectively, a sectional view of thedevice at a portion corresponding to the line X1-X1 of FIG. 15 in thecourse of the manufacture of the semiconductor device subsequent to thestep shown in FIG. 16.

As shown in FIGS. 15 and 16, a MISFET (hereinafter referred to simply asMIS) Q is formed, for example, at an active region surrounded by anisolation portion 4 on the main surface of a substrate (wafer) 1. Thesubstrate 1 is not made of an epitaxial wafer, but is made of anordinary semiconductor wafer. The isolation portion 4 has a so-calledtrench isolation structure, wherein it is formed by burying aninsulating film in a groove made in the main surface of the substrate 1.MIS Q has source and drain semiconductor regions 20 formed in the mainsurface of the substrate 1, a gate insulating film 21 formed on the mainsurface of the substrate 1, and a gate electrode 22 formed thereon.

The semiconductor region 20 is formed by introducing, for example,arsenic (As) or phosphorus (P), if MIS Q is an n-channel device, and itis formed by introducing, for example, boron (B) or boron difluoride(BF₂) for a MIS Q that is a p-channel device. The gate insulating film21 is made, for example, of a silicon oxide film, a silicon oxynitridefilm or a builtup structure of a silicon oxide film and a siliconnitride film. The gate electrode 22 is made, for example, of a singlefilm structure of a polysilicon film of low resistance, a so-calledpolycide structure wherein a silicide film is formed on a low resistancepolysilicon film, or a so-called polymetal structure wherein a metalfilm is provided on a low resistance polysilicon film through a barrierconductor film.

The substrate 1 has deposited, on the main surface thereof, aninsulating film made, for example, of a silicon oxide film, so as tocover the MIS Q therewith. This insulating film 23 is formed with awiring groove (opening for wiring) 23 a and a contact hole (opening forwiring) 24 b reaching the main surface of the substrate 1 from thebottom. As viewed in plane view, as shown in FIG. 15, the wiring groove24 a is formed as a band-shaped pattern extending in vertical directionsof FIG. 15. On the other hand, as viewed in section, as shown in FIG.16, the groove 24 a is formed as a rectangular groove having a depthextending to an intermediate position along the thickness of theinsulating film 23. The contact hole 24 b, as viewed in plane view, asshown in FIG. 15, is formed as a circular pattern whose diameter issmaller than the width (minor size) of the wiring groove 24 a, and part(part of the semiconductor regions 20 for source and drain) of the mainsurface of the substrate 1 is exposed from the bottom of the contacthole 24 b. As viewed in section, as shown in FIG. 16, the contact hole24 b is formed in such a state as to extend from the bottom surface ofthe wiring groove 24 a to the main surface of the substrate 1.

As shown in FIG. 17, a conductor film 15 and a conductor film 16 aresuccessively deposited in order from the lower layer on the main surfaceof the substrate 1 in the same manner as in the foregoing Embodiment 1.The conductor films 15, 16 are arranged in the same manner as inEmbodiment 1. In Embodiment 2, the conductor film 16 can be well buriedin the wiring groove 24 a and the contact hole 24 b in a space-freecondition, like Embodiment 1, and deposited while ensuring thecontinuity thereof. Subsequently, additional conductor films 16, 15 are,respectively, polished by a chemical mechanical polishing (CMP) method,thereby forming a buried wiring 25 having the conductor films 15, 16within the wiring groove 24 a and the contact hole 24 b.

(Embodiment 3)

In Embodiment 3, an application to a buried electrode (plug) formationtechnique is illustrated with reference to FIGS. 19 to 22. FIG. 19 is aplan view of the structure in the course of the manufacture of asemiconductor device of Embodiment 3, and FIG. 20 is a sectional viewtaken along the line X2-X2 of FIG. 19. FIGS. 21 and 22 are,respectively, a sectional view of the device at a portion correspondingto the line X2-X2 of FIG. 19 in the course of the manufacture of thesemiconductor device, subsequent to the step shown in FIG. 19.

As shown in FIGS. 19 and 20, an insulating film 26 that is made, forexample, of a silicon oxide film or the like is deposited on the mainsurface of a substrate (wafer) 1. This insulating film 26 has formedtherein a contact hole (opening for wiring) 24 b of a circular form, asseen in plane view, that reaches the main surface of the substrate 1. Asshown in FIG. 21, conductor films 15, 16 are successively deposited inorder from the lower layer on the main surface of the substrate 1, likethe foregoing Embodiments 1, 2. The conductor films 15, 16 are arrangedin the same manner as in Embodiments 1, 2. Accordingly, in Embodiment 3,the conductor film 16 can be well buried in the contact hole 24 b in aspace-free condition and deposited while ensuring the continuitythereof, like Embodiments 1, 2. Subsequently, additional conductor films16, 15 are, respectively, polished according to a CMP method or the liketo form a buried electrode (plug) 27 having the conductor films 15, 16inside the contact hole 24 b, as shown in FIG. 22.

(Embodiment 4)

In Embodiment 4, a modification of the foregoing Embodiment 3 isillustrated. FIG. 23 is a sectional view of the structure in the courseof the manufacture of a semiconductor device of Embodiment 4. Initially,after carrying out the steps of FIGS. 19 to 21 with respect to theforegoing Embodiment 3, the conductor films 15, 16 of FIG. 21 are,respectively, patterned through use of a resist pattern as an etchingmask according to ordinary photolithographic and dry etching techniquesto form wirings 28 having the conductor films 15, 16 on the insulatingfilm 26, as shown in FIG. 23. The wirings 28 are electrically connectedto the semiconductor regions 20 for the source and drain of MIS Qthrough the contact holes 24 b, respectively.

Although various embodiments of the invention which has been made by ushave been particularly described hereinabove, the invention should notbe construed as being limited to these embodiments, and manymodifications and changes may be possible without departing from thespirit of the invention.

For instance, although an application to a n-channel power MID has beendescribed by way of example in connection with the foregoing Embodiment1, the invention is not limited to this case, but may be applied to ap-channel power MIS.

Further, application to a power MIS having a trench gate electrodestructure has been described by way of example in connection withEmbodiment 1, but the invention is not limited to this application, andmay be applied to a power MID having a transverse gate electrodestructure formed on the main surface of the substrate.

Moreover, the annealing step 104 in FIG. 6 may be omitted. Moreparticularly, after deposition of the conductor film 16 a made ofaluminium or the like according to the low temperature sputtering methodas employed by way of example in Embodiment 1, the conductor films 16 b,16 c, each made of aluminium or the like, may be deposited in order fromthe lower layer by the heat sputtering method employed in the foregoingEmbodiment 1. Additionally, the steps 105, 106 in FIG. 6 may be omittedin some cases. More particularly, the conductor film 16 a that is madeof aluminium or the like may be deposited using a low temperaturesputtering method in Embodiment 1, followed by annealing (step 104 inFIG. 6) in the same manner as in Embodiment 1, thereby causing groovesor holes to be buried with the conductor film 16 a made of aluminium orthe like.

In the foregoing, applications to the manufacturing method of asemiconductor device having a power MIS, which is in the field ofutility to which the present invention is directed, have been described,but the invention should not be construed as being limited only to theseapplications, but it may be applied, for example, to the manufacture ofa semiconductor device having an IGBT (Insulated Gate BipolarTransistor) with a trench gate electrode structure. More particularly,the invention is applicable to the technique of forming a base electrodeand an emitter electrode of an IGBT, each made of aluminium or the like.Alternatively, the invention is also applicable to a power IC(integrated circuit) wherein cell arrays, which respectively have aplurality of transistor cells, each made of a transistor having a trenchgate electrode structure and control circuits, are mixed in the samesubstrate.

The effects of typical embodiments according to the invention will besummarized below.

A first conductor film, which has a structure capable of suppressing orpreventing the reaction between aluminium atoms and constituent atoms ina semiconductor substrate upon re-melting or thermal treatment of theconductor film made mainly of aluminium, is deposited on thesemiconductor substrate, including openings for wiring. Thereafter, theconductor film made mainly of aluminium flows and is charged into theopenings for wiring through a thermal treatment for re-melting after orduring the deposition of the conductor film, thus making it possible tosuppress or prevent a junction failure from occurring. This eventuallyleads to improved reliability of the resultant semiconductor device.

1. A semiconductor device including a plurality of MISFETs, comprising:a semiconductor substrate having a first conductivity type, serving as adrain of the plurality of MISFETs; a channel-forming region of theplurality of MISFETs, having a second conductivity type opposite to thefirst conductivity type, formed over the semiconductor substrate; aplurality of sources of the plurality of MISFETs, having the firstconductivity type, formed over the channel-forming region; a pluralityof trenches formed on a main surface of the semiconductor substrate andreaching the semiconductor substrate; a plurality of gate insulatingfilms of the plurality of MISFETs, formed on an inner wall of theplurality of trenches; a plurality of gates of the plurality of MISFETs,formed on the plurality of gate insulating films, wherein the pluralityof gates are electrically connected; an interlayer insulating filmformed over the plurality of gates; a source electrode, electricallyconnected with the plurality of source regions, formed over theinterlayer insulating film; a drain electrode, electrically connectedwith the semiconductor substrate, formed on a back surface of thesemiconductor substrate; wherein the plurality of gates are electricallyconnected; a plurality of contact holes exposing the plurality of thesources and the channel-forming region, formed in the interlayerinsulating film; and a plurality of conductive plugs buried in theplurality of contact holes, wherein the plurality of sources and thesource electrode are electrically connected via the plurality ofconductive plugs.
 2. A semiconductor device according to claim 1,wherein a plurality of grooves under the plurality of contact holes areformed in the main surface of the semiconductor substrate; wherein eachof the grooves are formed between the adjacent sources; wherein each ofthe grooves and contact holes are connected; and wherein the pluralityof plugs are buried in the plurality of grooves.
 3. A semiconductordevice according to claim 2, wherein side surfaces of the sources andthe plugs in the grooves are contacted.
 4. A semiconductor deviceaccording to claim 1, wherein the plurality of plugs are formed by:forming a conductive film in the plurality of contact holes and on amain surface of the interlayer insulating film; and removing a part ofthe conductive film, formed on the main surface of the interlayerinsulating film, using a CMP method.
 5. A semiconductor device accordingto claim 1, wherein the plurality of MISFETs comprise a power MISFET. 6.A semiconductor device according to claim 1, wherein the semiconductorsubstrate is comprised of a first semiconductor layer and a secondsemiconductor layer formed on the first semiconductor layer; and whereinthe second semiconductor layer is formed by an epitaxial growth method.7. A semiconductor device according to claim 1, wherein the first andsecond conductivity types are n-type and p-type, respectively.
 8. Asemiconductor device according to claim 1, wherein an extrinsic gatewiring is formed over the main surface of the semiconductor substrate;wherein the plurality of gates are electrically connected with theextrinsic gate wiring; and wherein the extrinsic gate wiring and theplurality of gates are made of a same layer.
 9. A semiconductor deviceaccording to claim 8, wherein a gate electrode is formed over theextrinsic gate wiring; wherein the gate electrode and the extrinsic gatewiring are electrically connected; and wherein the gate electrode andthe source electrode are made of a same layer.